1. Field of the Invention
The present invention relates to a flip chip package substrate suitable for bump on trace interconnection. The present invention is capable of providing high current density within power/ground network plane and input/output (I/O) area.
2. Description of the Prior Art
In order to ensure miniaturization and multi-functionality of electronic products or communication devices, semiconductor packages are required to be of small in size, multi-pin connection, high speed, and high functionality. Increased Input-Output (I/O) pin count combined with increased demands for high performance ICs has led to the development of flip chip packages.
Flip-chip technology uses bumps on chip to interconnect the package media such as package substrate. The flip-chip is bonded face down to the package substrate through the shortest path. These technologies can be applied not only to single-chip packaging, but also to higher or integrated levels of packaging in which the packages are larger and to more sophisticated substrates that accommodate several chips to form larger functional units. The flip-chip technique, using an area array, has the advantage of achieving the higher density of interconnection to the device and a very low inductance interconnection to the package.
FIG. 1 is a plan view showing a portion of the die attach surface of a conventional flip chip package substrate. The package substrate 20 has a die attach surface. The die attach surface at least includes a central area 201 for distributing power/ground network 200 and a peripheral area 202 encompassing the central area 201. Input/output (I/O) signal traces may be located in the peripheral area 202. The power/ground network 200 includes a comb-shaped conductive trace 210 and a comb-shaped conductive trace 220 disposed within the central area 201. For example, the comb-shaped conductive trace 210 is used to transmit power signal and the comb-shaped conductive trace 220 is used to transmit ground signal, or vice versa.
The comb-shaped conductive trace 210 is interdigitated with the comb-shaped conductive trace 220. A plurality of vias 212 for electrically connecting the comb-shaped conductive trace 210 to the underlying circuit are provided along the comb-shaped conductive trace 210. A plurality of vias 222 for electrically connecting the comb-shaped conductive trace 220 to the underlying metal circuit are provided along the comb-shaped conductive trace 220. In addition, a plurality of bumping sites (or bumping traces) 210a and a plurality of bumping sites 220a are provided along the comb-shaped conductive trace 210 and the comb-shaped conductive trace 220, respectively. These bumping sites 210a and 220a are used to interconnect with the respective bumps on a semiconductor die.
One drawback of the above-described conventional art is that the fine traces 210 and 220 cannot sustain large current density. One approach to solving this problem is to increase the widthwise dimension of the trace. However, this approach results in collapse of the bump disposed on the bumping site after reflow treatment, and thus leading to short circuit.